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1 standard ics segment-type lcd driver BU9729K the BU9729K is a driver for segmented liquid crystal displays, which enables connection with a microcomputer through a serial interface. 4-bit common output and an internal power supply circuit for lcd drive make it possible to configure a low-cost display system. 1) serial interface (8-bit length). 2) display ram: 72bits, internal (up to 72 segments can be displayed). 3) internal power supply circuit for liquid crystal drive. 4) display duty: 1 / 4. 5) low-voltage and low-current operation supported. block diagram serial interface address counter lcd driver bias circuit display data ram (dd ram) lcd segment driver 18bits lcd common driver 4bits com1 seg1 com2 com3 com4 sd command / data register command decoder timing generator common counter osc1 osc2 sck c / d cs v lcd seg2 seg18 v c v dd v ss features applications movie projectors, car audio equipment, telephones
2 standard ics BU9729K pin assignments seg10 seg11 25 seg12 seg13 seg14 seg15 seg16 seg17 seg18 osc1 1234567 fig.1 8 24 23 22 21 20 19 18 17 osc2 v ss v c v lcd v dd sck sd seg3 seg2 seg1 com4 com3 com2 com1 c / d cs seg4 seg5 seg6 seg7 seg8 seg9 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9
3 standard ics BU9729K pin descriptions i / o pin name function osc1 osc2 v ss v c v lcd v dd sck sd cs c / d com1 ~ com4 seg1 ~ seg18 i o i i i i o o pin no. 1 2 3 4 5 6 7 8 9 10 11 ~ 14 15 ~ 32 these are the i / o pins for the internal oscillator. resistance should be connected between the pins when the internal clock is operating. when an external clock is operating, input should be done from osc1, and osc2 should be left open. this is the v ss pin. this is the power supply pin for lcd drive. the condition v lcd ^ v c ^ v ss must be satisfied. this is the v dd pin. this is the shift lock input pin for serial data. the contents of the sd pin are read one bit at a time at the rising edge of this pin. this is the serial data input pin. display data and commands are input here. when this is 0 , display data is not displayed, and when 1 , the data is displayed. this is the chip select signal input pin. when this is low, sd input can be received. the sck counter is incremented at the timing at which cs goes from high to low. this is the signal input which recognizes whether the sd input consists of commands or display data. when the sck of the eighth clock rises, this pin judges the input to be display data if the le vel is low, and a command if the level is high. these are the common output pins for lcd drive. they are connected to the commons of the lcd panel. these are the segment output pins for lcd drive. they are connected to the segments of the lcd panel. absolute maximum ratings (ta = 25?, v ss = 0v) parameter symbol limits unit power supply voltage 1 power supply voltage 2 operating temperature storage temperature input voltage output voltage v dd v lcd pd t opr tstg v in v out ?0.3 ~ + 7.0 ?0.3 ~ + 7.0 * 1 400 * 2 ?20 ~ + 75 ?55 ~ + 125 ?0.3 ~ v dd + 0.3 ?0.3 ~ v dd + 0.3 v v mw c c v v * 1 the condition v lcd ^ v c ^ v ss must be satisfied. * 2 reduced by ? 4.0mw for each increase in ta of 1 c over 25 c . power dissipation
4 standard ics BU9729K recommended operating conditions (ta = 25?, v ss = 0v) parameter symbol unit max. typ. min. power supply voltage 1 power supply voltage 2 oscillation frequency v dd v lcd f osc v v khz conditions 2.5 2.5 5.5 5.5 36 the condition v lcd ^ v c ^ v ss must be satisfied. r f = 470k w electrical characteristics dc characteristics (unless otherwise noted, v dd = 2.5v to 5.5v, v ss = 0v, ta = 25?) parameter symbol min. typ. max. unit conditions lcd driver on-resistance * 1 input high level current 2 input low level current input capacitance current consumption input high level voltage input low level voltage v ih1 v il1 r on i il2 i ih c i i dd 0.8 v dd 0 ? 2 5 0.05 8 40 100 v dd 0.2 v dd 30 2 1 25 80 250 k w m a m a pf m a m a m a m a v v d v on = 0.1v v in = 0 v in = v dd while quiescent * 2 when all off is displayed for display operations * 3 for access operations * 4 applicable pin osc1, sd, sck, c / d, cs seg1 ~ 32, com1 ~ 4 osc1, sd, sck, c / d, cs osc1, sd, sck, c / d ,cs sd,sck, c / d, cs v dd * 1 the internal power supply impedance is not included in the lcd driver on-resistance. * 2 all input is fixed at either v dd or v ss . * 3 except for r f = 470k w and osc1, all input is fixed at v dd or v ss . * 4 r f = 470k w , fsck = 200khz. ac characteristics (unless otherwise noted, v dd = 2.5v to 5.5v, v ss = 0v, ta = 25?) t su2 t h2 t su3 t h3 t cch t sch 100 100 100 100 100 100 ns ns ns ns ns ns 8th rise of sck used as reference cs rise used as reference 8th fall of sck used as reference * 5 should satisfy either one of these conditions. parameter symbol min. typ. max. unit conditions sck rise time sck fall time sck cycle time command wait time sck pulse width high sck pulse width low data setup time data hold time cs pulse width high cs pulse width low cs setup time cs hold time c / d setup time c / d hold time c / d-cs time * 5 c / d-sck time * 5 t tlh t thl t cyc t wait t wh1 t wl1 t su1 t h1 t wh2 t wl2 800 800 300 300 100 100 300 6400 100 100 ns ns ns ns ns ns ns ns ns ns
5 standard ics BU9729K input / output circuits pin name i / o equivalent circuit pin name com1 ~ com4 gnd v dd in i / o equivalent circuit osc1 osc2 sd sck c / d cs i o i seg1 ~ seg18 o gnd v dd osc1 osc2 v lcd out gnd v lcd
6 standard ics BU9729K timing charts c / d cs sck t wl2 t wh2 sd sck d 7 sd t h2 d 6 d 0 d 7 t su2 t wh1 t wl1 t sch t cyc t su3 t h3 t cch t su1 t h1 t tlh1 t thl t cyc t wa / t fig. 2 interface timing fig. 3 command cycle data format serial data is transmitted using four-line clock synchronous transmission. serial data with a length of eight bits is input synchronized to sck. if c / d is high at the rise of the 8 nth clock of sck, the serial data is recognized as a command, and if c / d is low, the serial data is recognized as display data. serial data is input sequentially, starting from the msb.
7 standard ics BU9729K detailed explanation of commands the following commands (c / d is high at the 8 nth clock of sck) are available for the BU9729K. (1) address set 0 0 0aaaaa lsb msb address data displayed in binary format as aaaaa is set for the address counter. the address is incremented by two each time input of the display data (8 bits of data) is completed. (2) display on 0 01 lsb * : don't care msb ***** all displays light, regardless of the contents of the display data ram (ddram). at this point, the contents of the ddram do not change. (3) display off 0 10 lsb * : don't care msb ***** all displays go out, regardless of the contents of the ddram. at this point, the contents of the ddram do not change. (4) display start 0 11 lsb * : don't care msb * **** the display begins, in accordance with the contents of the ddram. (5) display data ram (ddram) write 1 0 0 dddd lsb * : don't care msb * the binary 4-bit data dddd is written to the ddram. the address is that specified by the address set command. after this command is executed, the address is automat- ically incremented by + 1.
8 standard ics BU9729K (6) reset 1 10 * lsb * : don't care msb **** this command should be executed after the power supply has been turned on and before any other command is executed. this command causes the BU9729K to initialize the following: display off address counter reset description of functions (1) register the BU9729K has an 8-bit command / data register. serial data is read in 8-clock units of sck. if the data read into the register is displayed data (c / d is low at the eighth clock of sck), it is written to the ddram. if it is command data (c / d is high at the eighth clock of sck), it is output to the command decoder to control the BU9729K. (2) address counter the address counter indicates ddram addresses. when the address set command is written to a command or data register, the address data is sent automatically to the address counter. after data has been written to the ddram, the address counter increments automatically by either + 1 or + 2. the amount by which the counter increments is determined automatically, based on the following status. ddram 8-bit writing (c / d is low at the eighth clock of sck) ? + 2 ddram 4-bit writing (c / d is high at the eighth clock of sck) ? + 1 when the address counter has counted to the address 11h, it becomes 00h the next time it is incremented. (3) display data ram (ddram) the display data ram (ddram) is used to store display data. it has a capacity of 18 addresses 4 bits. the relationship between the ddram and the display position is shown below. dd ram address 00 11 10 0f 01 02 03 04 05 06 07 1 2 3 0 com2 com3 com4 com1
9 standard ics BU9729K ddram addresses set for the address counter are in hexadecimal format, and are displayed as shown below. ac 4 ac 3 ac 2 ac 1 ac 0 lsb msb (example) when the ddram address is "11" (display position: seg18) 1 1 0001 lsb msb 1 display data input to the command / data register (c / d = low) is divided into the first four bits and the last four bits, with the specified ddram address being written to the first four, and the specified address + 1 being written to the last four. the four bits of display data are written sequentially to the bits of the ddram, starting from the msb on both sides. specified address (bit3 bit0) specified address + 1 (bit3 bit0) d7 d6 d5 d4 d3 d2 d1 d0 lsb msb when a ddram write command is input (c / d = high), the four bits of display data in the ddram write command are written to the specified ddram address. the four bits are written sequentially, starting from the msb, to the bits of the ddram, starting with the msb of the ddram. ddram write command display data (bit3 bit0) 1 00 * d3 d2 d1 d0 lsb msb (4) timing generator connecting rf between osc1 and osc2 causes oscillation of the internal oscillator circuit and generates a display timing signal. operation can also be initiated by inputting an external clock. osc1 osc2 rf (rf can be used to change the oscillation frequency.) fig. 4 rf oscillator circuit osc1 osc2 exit clock input fig. 5 external clock input open
10 standard ics BU9729K (5) lcd driver power supply the lcd driver power supply is generated by the BU9729K. v 1 = 2 ?v c / 3, v2 = v c / 3 is generated internally. v dd v lcd v c v ss fig. 6 example of power supply connection (6) lcd drive circuit the lcd drive circuit is configured of 4 common drivers and 18 segment drivers. when oscillation begins, any effec- tive common output automatically outputs a selective waveform, while the others output non-selective waveforms. segment output automatically outputs drive waveforms, based on the display data and common counter. the com- mon and segment output waveforms are shown in the following examples.
11 standard ics BU9729K lcd drive waveforms com1 v c v 1 v 2 v ss frame interval com2 v c v 1 v 2 v ss com3 v c v 1 v 2 v ss com4 v c v 1 v 2 v ss v c v 1 v 2 v ss v c v 1 v 2 v ss seg1 seg18 ~ v c v 1 v 2 v ss v c v 1 v 2 v ss v c v 1 v 2 v ss com1 com2 com3 com4 0 0 0 0 (no segn corresponding from com1 to com4 are displayed.) 1 0 0 0 (only segn corresponding to com1 are displayed.) 0 1 0 0 (only segn corresponding to com2 are displayed.) 0 1 0 1 (only segn corresponding to com2 and com4 are displayed.) 1 1 1 1 (all segn corresponding from com1 to com4 are displayed.) fig. 7
12 standard ics BU9729K external dimensions (units: mm) qfp32 0.15 0.4 0.1 24 17 16 9 8 1 25 32 7.0 0.2 9.0 0.3 7.0 0.2 9.0 0.3 0.4 0.05 1.45 0.1 0.15 0.1 0.8 0 < t on < 10ms v dd ^ 2.5v v dd < 0.3v t wait < 1ms instruction receipt possible v dd has to satisfy the following conditions.

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